View UPD98401A_5698.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD98401A
ATM SAR CHIP
DESCRIPTION
The PD98401A (NEASCOT-S15TM) is a high-performance SAR chip that segments and reassembles ATM cells. This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor, network hub, or router. The PD98401A conforms to the ATM Forum Recommendation, and provides the functions of the AAL-5 SAR sublayer and ATM layer. The PD98401A is compatible with its predecessor, PD98401, in terms of hardware and software. Functions are explained in detail in the following User's Manual. Be sure to read this manual when designing your system.
PD98401A User's Manual: S12054E
FEATURES
* Conforms to ATM Forum * AAL-5 SAR sublayer and ATM layer functions * Hardware support of AAL-5 processing * Processing of non-AAL-5 traffic (AAL-3/4 cell, OAM cell, RM cell) by software with raw cell processing function * Hardware support of comparison/generation of CRC-10 for non-AAL-5 traffic * Supports up to 32K virtual channels (VC) * Provided with 16 traffic shapers that carry out transmission scheduling (control of average rate/peak rate) so as to set different transmission rate for each VC * Interface and commands for controlling PHY device * Employs "UTOPIA interface" as cell data interface with PHY device - Octet-level handshake - Cell-level handshake * 32-bit general-purpose bus interface * High-speed DMAC (supports 1-, 2-, 4-, 8-, 12-, and 16-word burst) * JTAG boundary scan test function (IEEE1149.1) * CMOS technology * +5 V single power source Remark In this document, an active low pin is indicated by xxx_B (_B after a pin name).
The information in this document is subject to change without notice.
Document No. S12100EJ3V0DS00 (3rd edition) Date Published February 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1997
PD98401A
ORDERING INFORMATION
Part Number Package 208-pin plastic QFP (fine pitch) (28 x 28 mm)
PD98401AGD-MML
SYSTEM CONFIGURATION
ATM interface card
Reception
PD98401A
Control memory
PD98402A
PMD Transmission
ATM network
Bus interface
I/O bus
BLOCK DIAGRAM
Receive data FIFO
PHY interface reception block
PHY device transmission block
Reception controller
System port
DMA controller and host interface
Sequencer
Control memory interface
Control memory
Transmission controller PHY interface transmission block PHY device reception block
Transmit data FIFO (10 cells)
2
Data Sheet S12100EJ3V0DS00
PD98401A
PIN CONFIGURATION
Rx7-Rx0 RCLK RENBL_B RSOC PHY interface EMPTY_B/RxCLAV Tx7-Tx0 TCLK TENBL_B TSOC FULL_B/TxCLAV PHRW_B PHOE_B PHCE_B PHINT_B AD31-AD0 PAR3-PAR0 OE_B SIZE2-SIZE0 DR/W_B ATTN_B GNT_B Bus interface RDY_B ABRT_B ERR_B SR/W_B SEL_B ASEL_B CLK RST_B INTR_B Slave Master
CD31-CD0 CPAR3-CPAR0 CA17-CAD CWE_B COE_B CBE_B3-CBE_B0 INITD Control memory interface
DBVC DBMD DBML DBMF DBMR Bus monitoring
JDO JDI JCK JMS JRST_B JTAG boundary scan interface
TRF_B
Test pin (fixed to low level)
VDD VDD GND Power supply
Data Sheet S12100EJ3V0DS00
3
PD98401A
PIN CONFIGURATION (Top View)
208-pin plastic QFP (fine pitch) (28 x 28 mm)
VDD DBVC DBMR GND VDD JRST_B JMS JDI JDO GND VDD JCK GND VDD DBMF DBML DBMD GND VDD TRF_B INTID COE_B CWE_B CBE_B0 CBE_B1 VDD GND CBE_B2 CBE_B3 CA0 CA1 CA2 CA3 GND VDD CA4 CA5 CA6 CA7 CA8 CA9 CA10 GND VDD CA11 CA12 CA13 CA14 CA15 CA16 CA17 VDD
GND GND AD31 AD30 AD29 AD28 AD27 GND AD26 AD25 AD24 AD23 AD22 GND VDD AD21 AD20 AD19 AD18 AD17 GND AD16 AD15 AD14 AD13 GND VDD AD12 RST_B VDD GND CLK GND VDD AD11 AD10 AD9 AD8 AD7 GND VDD AD6 AD5 AD4 AD3 AD2 AD1 AD0 PAR3 PAR2 GND GND
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
GND GND CPAR0 CPAR1 CPAR2 CPAR3 GND CD0 CD1 CD2 CD3 CD4 CD5 CD6 VDD GND CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 GND VDD CD16 CD17 CD18 CD19 CD20 VDD GND CD21 CD22 CD23 CD24 CD25 CD26 CD27 GND VDD CD28 CD29 CD30 CD31 PHRW_B PHOE_B PHINT_B GND GND
4
VDD PAR1 PAR0 OE_B SIZE2 VDD GND SIZE1 SIZE0 DR/W_B ATTN_B GND_B RDY_B ABRT_B ERR_B SR/W_B SEL_B ASEL_B INTR_B VDD GND Rx7 Rx6 Rx5 Rx4 VDD GND Rx3 Rx2 Rx1 Rx0 RCLK RENBL_B RSOC EMPTY_B/RxCLAV FULL_B/TxCLAV TSOC TENBL_B GND TCLK GND VDD Tx7 Tx6 Tx5 Tx4 Tx3 Tx2 Tx1 Tx0 PHCE_B VDD
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
Data Sheet S12100EJ3V0DS00
PD98401AGD-MML
PD98401A
PIN NAMES
ABRT_B AD31_AD0 ASEL_B ATTN_B CA17-CA0 CD31-CD0 CLK COE_B CPAR3-CPAR0 CWE_B DBMD DBMF DBML DBVC DBMR DR/W_B ERR_B FULL_B/TxCLAV GND GNT_B INITD INTR_B JCK JDI JDO JMS JRST_B OE_B PAR3-PAR0 : Abort : Address/Data : Slave Address Select : Attention/Burst Frame : Control Memory Address : Control Memory Data : Clock : Control Memory Output Enable : Control Memory Parity : Control Memory Write Enable : DMA Bus Monitor Data : DMA Bus Monitor First : DMA Bus Monitor Last : DMA Bus Monitor VC : DMA Bus Monitor Remaining : DMA Read/Write : Error : PHY Buffer Ful : Ground : Grant : Initialization Disable : Interrupt : JTAG Test Pin : JTAG Test Pin : JTAG Test Pin : JTAG Test Pin : JTAG Test Pin : Output Enable : Bus Parity PHCE_B PHINT_B PHOE_B PHRW_B RCLK RDY_B RENBL_B RSOC RST_B Rx7-Rx0 SLE_B SIZE2-SIZE0 SR/W_B TCLK TENBL_B TSOC TRF_B Tx7-Tx0 VDD : PHY Chip Enable : PHY Interrupt : PHY Output Enable : PHY Read/Write : Receive Clock : Target Ready : Receive Enable : Receive Start Cell : Reset : Receive Data Bus : Slave Select : Burst Size : Slave Read/Write : Transmit Clock : Transmit Enable : Transmit Start of Cell : Delay Select : Transmit Data Bus : Power Supply
CBE_B3_CBE_B0 : Local Port Byte Enable
EMPTY_B/RxCLAV : PHY Output Buffer Empty
Data Sheet S12100EJ3V0DS00
5
PD98401A
CONTENTS
1. PIN FUNCTION ..................................................................................................................................... 7 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 PHY Device Interface Pin ............................................................................................................. 7 Bus Interface Pins ........................................................................................................................ 9 Bus Monitor Pins ........................................................................................................................ 12 Control Memory Interface Pins.................................................................................................. 13 JTAG Boundary Scan Pins ........................................................................................................ 14 Test Pin........................................................................................................................................ 14 Power Supply and Ground Pins................................................................................................ 14 Pin Status During and After Reset ............................................................................................ 15
2. DIFFERENCES FROM PD98401.................................................................................................... 16 2.1 Additional Functions.................................................................................................................. 16 TM 2.2 Differences from PD98401 (NEASCOT-S10 )........................................................................ 16 3. ELECTRICAL SPECIFICATIONS ...................................................................................................... 17 4. PACKAGE DRAWINGS ...................................................................................................................... 33 5. RECOMMENDED SOLDERING CONDITIONS.................................................................................. 34
6
Data Sheet S12100EJ3V0DS00
PD98401A
1. PIN FUNCTION
The PD98401A is housed in a package having 208 pins, of which 152 pins are function pins and 56 pins are VDD and GND pins.
1.1 PHY Device Interface Pin
PHY device interfaces include a UTOPIA interface through which the PD98401A transfers ATM cells with a PHY device, and a PHY control interface by which the PD98401A controls the PHY device.
(1)
UTOPIA interface (1/2)
Pin No. 74 - 77 80 - 83 I/O I I/O Level TTL Receive Data Bus. Rx7 through Rx0 constitute an 8-bit input bus which inputs data received from a network in byte format from a PHY device. The PD98401A loads data in at the rising edge of RCLK. I TTL Receive Start Cell. The RSOC signal is input in synchronization with the first byte of the cell data from a PHY device. This signal remains high while the first byte of the header is input to Rx7 through Rx0. Function
Pin Name Rx7-Rx4 Rx3-Rx0
RSOC
86
RENBL_B
85
O
CMOS
Receive Enable. The RENBL_B signal indicates to a PHY device that the PD98401A is ready to receive data in the next clock cycle. This signal goes high during and after reset.
EMPTY_B/ RxCLAV
87
I
TTL
PHY Output Buffer Empty/Rx Cell Available. This signal notifies the PD98401A that there is no cell data to be transferred in the receive FIFO and that no receive data can be supplied to the PHY device. When the UTOPIA interface is in the octet-level handshake mode, this signal serves as EMPTY_B, indicating that the data on Rx7 through Rx0 are invalid in the current clock cycle. In the cell-level handshake mode, it serves as RxCLAV, indicating that there is no cell to be supplied next after the transfer of the current cell is completed.
RCLK
84
O
CMOS
Receive Clock. This is a synchronization clock used to transfer cell data with the PHY cell device at the recieve side. The system clock input to the CLK pin is output from this pin as is, immediately after reset.
Tx7-Tx0
95 - 102
O
CMOS
Transmit Data Bus. Tx7 through Tx0 constitute an 8-bit output bus which outputs transmit data in byte format to a PHY device. The PD98401A outputs data at the rising edge of TCLK.
TSOC
89
O
CMOS
Transmit Start of Cell. The TSOC signal is output in synchronization with the first byte of transmit cell data.
Data Sheet S12100EJ3V0DS00
7
PD98401A
(2/2)
Pin Name TENBL_B Pin No. 90 I/O O I/O Level CMOS Transmit Enable. The TENBL_B signal indicates to a PHY device that data has been output to Tx7 through Tx0 in the current clock cycle. This signal remains high during reset and after reset. FULL_B/ TxCLAV 88 I TTL PHY Buffer Full/Tx Cell Available. The FULL_B signal notifies the PD98401A that the input buffer of the PHY device is full and that the device can receive no more data. When the UTOPIA interface is in the octet-level handshake mode, the PHY device inputs an inactive level to receive cell of data. In the celllevel handshake mode, this signal indicates that the PHY device can receive all the next one cell of data after the current cell has been completely transferred TCLK 92 O CMOS Transmit Clock. This is a synchronization clock used to transfer cell data with the PHY device at the transmission side. The system clock input to the CLK pin is output from this pin as is. Function
(2)
PHY device control interface
Pin No. 109 I/O O I/O Level CMOS PHY Read/Write. The PD98401A indicates the direction in which the PHY device is controlled, by using PHRW_B. This signal goes low after reset. 1: Read 0: Write Function
Pin Name PHRW_B
PHOE_B
108
O
CMOS
PHY Output Enable. The PD98401A enables output from the PHY device by making PHOE_B low
PHCE_B
103
O
CMOS
PHY Chip Enable. The PD98401A makes PHCE_B low to access a PHY device. This signal goes high after reset.
PHINT_B
107
I
TTL
PHY Interrupt. This is an interrupt input signal from a PHY device. The PHY device indicates to the PD98401A that it has an interrupt source, by inputting a low level to PHINT_B. This signal goes high after reset.
8
Data Sheet S12100EJ3V0DS00
PD98401A
1.2 Bus Interface Pins
The bus interface is a general-purpose bus interface compatible with most generally used I/O buses (such as PCI, S bus, GIO, and AP bus). (1/3)
Pin Name AD31-AD27 AD26-AD22 AD21-AD17 AD16-AD13 AD12 AD11-AD7 AD6-AD0 PAR3 PAR2 PAR1 PAR0 Pin No. 3-7 9 - 13 16 - 20 22 - 25 28 35 - 39 42 - 48 49 50 54 55 I/O 3-state TTL in CMOS out I/O I/O 3-state I/O Level TTL in CMOS out Address/Data. AD31 through AD0 constitute a 32-bit address/data bus. These pins are I/O pins multiplexing an address bus and a data bus. At the first clock of input/output, AD31 through AD0 transfer an address. They transfer data at the second clock and onward. The AD bus goes into a high-impedance state when the PD98401A does not access the bus. Bus Parity. PAR pins indicate the parity of AD31 through AD0. A parity check mode is set by GMR. Enabling or disabling parity, odd or even parity, and word or byte parity can be specified. If byte parity is specified, PAR3 indicates the parity of AD31 through AD24, and PAR0 indicates the parity of AD7 through AD0. If word parity is specified, PAR3 serves as an input/output pin. It serves as an output pin when an address is output and when data is written, and as an input pin when data is read. When the PD98401A does not access the bus, PAR3 through PAR0 go into a high-impedance state. Pull up these pins when they are not used. OE_B 56 I TTL Output Enable. When this pin is low, the PD98401A uses AD31 through AD0 and PAR3 through PAR0 as 3-state I/O pins. These pins go into a highimpedance state while a high level is being input to OE_B. This pin is an option pin. Fix this pin to low level in a system where it is not necessary to forcibly set the bus of the PD98401A in a highimpedance state by controlling this pin. SIZE2 SIZE1 SIZE0 57 60 61 O CMOS Burst Size. SIZE2 through SIZE0 indicate the size of the current DMA transfer. These pins are used to interface a bus (such as S bus) requiring clear burst size. Function
SIZE2 0 0 0 0 1 1 1 1
SIZE1 0 0 1 1 0 0 1 1
SIZE0 0 1 0 1 0 1 0 1
Function 1-word transfer 2-word burst 4-word burst 8-word burst 16-word burst 12-word burst Undefined Reception side byte alignment
Data Sheet S12100EJ3V0DS00
9
PD98401A
(2/3)
Pin Name DR/W_B Pin No. 62 I/O O I/O Level CMOS DMA Read/Write. DR/W_B indicates the direction of DMA access. 1: Read access 0: Write access This pin is set to 1 after reset. ATTN_B 63 O CMOS Attention/Burst Frame (DMA request). The PD98401A makes the ATTN_B signal low when it performs a DMA operation. The ATTN_B signal becomes inactive at the rising edge of CLK when the data to be transferred by means of DMA has decreased to 1 word. GNT_B 64 I TTL Grant. The GNT_B signal inputs a low level when the bus arbiter grants the PD98401A use of the bus in response to a DMA request from the PD98401A. The PD98401A recognizes that it has been granted use of the bus and starts DMA operation when the GNT_B signal goes low (active). Make sure that the GNT_B signal falls at least one system clock cycle after the rising of the ATTN_B signal. The GNT_B signal must be returned to the high (inactive) level before the PD98401A makes the ATTN_B signal low (active) to issue the next DMA cycle request. RDY_B 65 I TTL Target Ready. RDY_B indicates to the PD98401A in the DMA cycle that the target device is ready for input/output. During the DMA read operation of the PD98401A, the RDY_B signal is made low if valid data is on AD31 through AD0. During the DMA write operation of the PD98401A, the RDY_B signal is made low if the target device is ready for receiving data. The sampling timing of the RDY_B and ABRT_B signals of the PD98401A can be advanced by one clock (early mode) by using an internal register (GMR register). ABRT_B 66 I TTL Abort. ABRT_B is used to abort the DMA transfer cycle. If this signal goes low while data is being transferred in the DMA cycle, DMA transfer is aborted in that cycle, and the ATTN_B signal is briefly deasserted inactive. After that, the PD98401A asserts the ATTN_B signal active again, and resumes burst transfer from the data at which the DMA transfer was aborted. While a low level is input to ABRT_B, the RDY_B signal is ignored. The user can advance the sampling timing of the RDY_B and ABRT_B signals of the PD98401A by one clock (early mode) by using an internal register (GMR register). Pull up this pin when it is not used. ERR_B 67 I TTL Error. This pin is used by a device that manages the bus to stop the operation of the PD98401A when occurrence of an error is detected on the system bus. When a low level is input to this pin, the PD98401A stops all bus operations, sets the system bus error bit (bit 25) of the GSR register (when not masked), and generates an interrupt. Pull up this pin when it is not used. Function
10
Data Sheet S12100EJ3V0DS00
PD98401A
(3/3)
Pin Name SR/W_B Pin No. 68 I/O I I/O Level TTL Slave Read/Write. The SR/W_B signal determines the direction in which the slave is accessed. 1: Read access 2: Write access SEL_B 69 I TTL Slave Select. This signal goes low (active) when the PD98401A is accessed as a slave. The SEL_B signal must goes low as soon as or after the ASEL_B signal has gone low. An inactive period of at least 2 system clock cycles must be inserted between when the SEL_B signal has become inactive and when it becomes active again. ASEL_B 70 I TTL Slave Address Select. The ASEL_B signal is used to select the direct address register of the PD98401A. When a low level is input to ASEL_B, the PD98401A samples the AD bus at the first rising edge of CLK. CLK 32 I TTL Clock. This pin inputs the system clock. Input a clock in a range of 8 to 33 MHz. RST_B 29 I TTL Reset. The RST_B signal initializes the PD98401A (on starting, etc.). After reset, the PD98401A can start normal operation. When a low level is input to RST_B, the internal state machine and registers of the PD98401A are reset, and all 3-state signals go into a highimpedance state. The reset input is asynchronous. When this signal is input during operation, the operating status at that time is lost. Hold RST_B low at least for the duration of one clock. After reset, do not access the PD98401A for at least 20 clock cycles. INTR_B 71 O Nch opendrain output Interrupt. This is an open-drain signal and must be pulled up. INTR_B informs the CPU that the interrupt bit (unmasked) of the GSR register is set. Function
Data Sheet S12100EJ3V0DS00
11
PD98401A
1.3 Bus Monitor Pins
The bus monitor pins indicate the type of data under DMA transfer. These five pins are enabled when the BME bit of the GMR register is set to 1; they go into a high-impedance state when the BME bit is 0.
Pin Name DBMD Pin No. 192 I/O O 3-state I/O Level CMOS DMA Bus Monitor Data. This pin indicates that the payload of an AAL-5 cell is under DMA transfer. This pin is enabled when the BME bit of the GMR register is set to 1, and goes into a high-impedance state when the BME bit is 0. The DBMD signal changes in synchronization with the falling of the ATTN_B signal. The high level of this signal indicates that the payload of an ALL-5 packet transmit/receive cell is under DMA transfer, and low level indicates that the other data is being transferred. CMOS DMA Bus Monitor Last. If one-word data currently under DMA transfer satisfies any of the following conditions, this pin goes high in synchronization with output of the data.
* * *
Function
DBML
193
O 3-state
Last 1 word of last cell of AAL-5 packet 1-word data to be written to last word of receive buffer Last 1-word data of last cell of receive packet in which MAX. NUMBER OF SEGMENTS error has occurred
When this pin is low, it indicates that the data is other than above. This pin is enabled when the BME bit of the GMR register is set to 1; it goes into a high-impedance state when the bit is 0. DBMF 194 O 3-state CMOS DMA Bus Monitor First. This pin indicates that the data under DMA transfer is the start cell of a receive AAL-5 packet. This pin is enabled when the BME bit of the GMR register is set to 1; it goes into a high-impedance state when the bit is 0. This pin goes high in synchronization with the last word data of the first cell of an AAL-5 packet. CMOS DMA Bus Monitor Remaining. This pin indicates that the number of cells remaining in the transmit buffer is equal to, or has dropped below the value assigned to the RCS register. This pin is enabled when the BME bit of the GMR register is set to 1; it goes into a high-impedance state when the bit is 0. CMOS DMA Bus Monitor VC. This pin indicates that the data currently being transferred by DMA is that of the VC for which the VCP bit in the receive VC table is set to 1. This pin is asserted active in synchronization with the falling of ATTN_B. It is enabled when the BME bit of the GMR register is set to 1, and goes into a high-impedance state when the bit is 0.
DBMR
206
O 3-state
DBVC
206
O 3-state
12
Data Sheet S12100EJ3V0DS00
PD98401A
1.4 Control Memory Interface Pins
These pins constitute an interface through which the PD98401A accesses an external control memory and a PHY device. A 18-bit address bus and a 32-bit data bus are used. The control memory of the host is accessed only via this interface.
Pin Name CD31-CD28 CD27-CD21 CD20-CD16 CD15-CD7 CD6-CD0 CPAR3CPAR0 Pin No. 110-113 116-122 125-129 132-140 143-149 151-154 I/O TTL in, CMOS out Control Memory Parity. CPAR3 through CPAR0 indicate the parity of CD31 through CD0 in 8bit units. In the read cycle, the PD98401A checks the parity (when enabled). In the write cycle, CPAR3 through CPAR0 output the parity. Pull up these pins when they are not used. Control Memory Address. CA17 through CA0 constitute an 18-bit address bus. They output an address to the control memory or a PHY device during read/write operation. O CMOS Control Memory Write Enable. CWE_B signal indicates the direction in which the control memory is accessed. 1: Read access 2: Write access COE_B 187 O CMOS Control Memory Output Enable COE_B enables or disables data output of the control memory. CBE_B3 CBE_B2 CBE_B1 CBE_B0 INITD 180 181 184 185 188 I TTL Initialization Disable. The INITD signal is used to disable automatic initialization of the control memory during chip test. During normal operation other than test, directly connect INITD to GND. O CMOS Local Port Byte Enable. CBE_B3 through CBE_B0 indicate the byte on the control port to be read or written. I/O I/O 3-state I/O Level TTL in, CMOS out Control Memory Data. CD31 through CD0 are 3-state I/O pins and constitute a 32-bit data bus which is used to transfer data with the control memory or a PHY device. Function
CA17-C11 CA10-CA4 CA3-CA0 CWE_B
158-164 167-173 176-179 186
O
CMOS
Data Sheet S12100EJ3V0DS00
13
PD98401A
1.5 JTAG Boundary Scan Pins
Pin Name JDI Pin No. 201 I/O I I/O Level TTL JTAG Test Data Input. The JDI pin is used to input data to the JTAG boundary scan circuit register. Normally, fix this pin to high or low level. JDO 200 O 3-state CMOS JTAG Test Data Output. The JDO pin is used to output data from the JTAG boundary scan circuit register. It changes output at the falling edge of the clock input to the JCK pin. Normally, leave this pin open. JCK 197 I TTL JTAG Test Clock. This pin is used to supply a clock to the JTAG boundary scan circuit register. Normally, fix this pin to a high or low level. JMS 202 I TTL JTAG Test Mode Select. Normally, fix this pin to a high or low level. JRST_B 203 I TTL JTAG Test Reset. This pin initializes the JTAG boundary scan circuit register. Normally, fix this pin to a low level. Function
1.6 Test Pin
Pin Name TRF_B Pin No. 189 I/O I I/O Level TTL Function This pin is used to test the internal circuitry of the chip. 0: Normal operation 1: Test Normally, directly connect this pin to ground and fix it to a low level.
1.7 Power Supply and Ground Pins
Pin Name VDD Pin No. 15, 27, 30, 34, 41, 53, 58, 72, 78, 94, 104, 114, 124, 130, 142, 157, 165, 174, 183, 190, 195, 198, 204, 208 1, 2, 8, 14, 21, 26, 31, 33, 40, 51, 52, 59, 73, 79, 91, 93, 105 ,106, 115, 123, 131, 141, 150, 155, 156, 166, 175, 182, 191, 196, 199, 205 I/O Power supply (24 pins) These 24 VDD pins supply a voltage of +5 V 5% to the chip. Function
GND
Ground (32 pins) Connect these pins to ground.
14
Data Sheet S12100EJ3V0DS00
PD98401A
1.8 Pin Status During and After Reset
Pin AD0-AD31 PAR0-PAR3 SIZE0-SIZE2 DR/W_B ATTN_B INTR_B CA17-CA0 CD0-CD31 CWE_B COE_B CBE_B3-CBE_B0 PHRW_B PHOE_B PHCE_B RCLK RENBL_B Tx0-Tx7 TCLK TENBL_B TSOC JDO DBMD DBML DBMF DBMR DBVC During Reset Hi-Z (input mode) Hi-Z (input mode) 0 1 1 1 (however, pulled up) 0 All 0 (output mode) 1 1 All 1 0 1 1 CLK output 1 All 0 CLK output 1 0 Hi-Z (3-state) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z After Reset Hi-Z (input mode) Hi-Z (input mode) 0 1 1 1 (however, pulled up) 0 All 0 (output mode) 1 1 (repetition of high/low) All 1 0 1 1 CLK output 0 All 0 CLK output 1 0 Hi-Z (3-state) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Data Sheet S12100EJ3V0DS00
15
PD98401A
2. DIFFERENCES FROM PD98401
2.1 Additional Functions
The PD98401A is compatible with the PD98401 in terms of hardware and software. However, the PD98401A has the following additional functions as compared with the PD98401. additional functions are enabled by the setting of the GMR register. (1) DMA 12-word burst cycle (2) Byte alignment transfer function of receive data buffer (3) Bus monitor pin (4) Mode to insert idle cell for transmission rate adjustment (5) New scheduling function Aggregate mode (6) Receive packet size indication (cell units/Length mode added) (7) Cell-level support of UTOPIA interface (8) AAL-3/4 traffic assist function (9) JTAG boundary scan support All the
2.2 Differences from PD98401 (NEASCOT-S10TM)
(1) Increased receive FIFO size
PD98401
: 10 cells
PD98401A : 23 cells
(2) Cell processing of PTI field (1XX)
PD98401
: Receives cells other than those of OAM F5 pattern (101, 100) as user data cells.
PD98401A : Processes as raw cell of 1XX pattern. Stores in pool 0.
(3) Changing transmission mode of unassigned cell The PD98401 starts transmitting unassigned cells immediately after power application and continues transmitting the unassigned cells while there is no active transmission VC. It also has a function to stop transmitting unassigned cells while there is not an active VC, by using the UCE bit of the GMR register. The PD98401A deletes this UCE bit function, makes the TENBL_B signal inactive on power application and when there is no active VC, and does not transmit unassigned cells. The PD98401A transmits unassigned cells only when there is an active VC and when the unassigned cell generator function is enabled.
16
Data Sheet S12100EJ3V0DS00
PD98401A
3. ELECTRICAL SPECIFICATIONS
An asterisk (*) mark indicates portion which have been revised from PD98401.
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Symbol VDD VI IO1 IO2
Note 1
Condition
Ratings -0.5 to +6.5 -0.5 to VDD +0.5 24 36 0 to +80 -65 to +150
Unit V V mA mA C C
Output current Operating ambient temperature
Storage temperature
Note 2
TA Tstg
Caution
If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings.
DC Characteristics (TA = 0 to +80 C, VDD = 5 V 5 %)
Parameter Low level input voltage High level input voltage Symbol VIL VIH1 VIH2 High level output voltage VOH1 VOH2 Low level output voltage VOL1 VOL2 Supply current Input leakage current Output leakage current
Note 1
Condition
MIN. -0.5
TYP.
MAX. +0.8 VDD + 0.5 VDD + 0.5
Unit V V V V V
Except pins RST_B or CLK Pins RST_B or CLK IOH = -4.0 mA IOH = -6.0 mA IOL = 8.0 mA IOL = 12.0 mA Normal operation VI = VDD or GND Vo = VDD or GND
+2.2 +3.3 VDD x 0.7 VDD x 0.7
Note 2
Note 1
0.4 0.4 350 -10 -10 500 +10 +10
V V mA
Note 2
IDD ILI IOZ
A A
Notes 1. IO1, VOH1 and VOL1 apply to the following pins: CD31 - CD0, CPAR3 - CPAR0, CA17 - CA0, CBE_B3 - CBE_B0, CWE_B, COE_B, RCLK, RENBL_B, TSOC, TENBL_B, TCLK, Tx7 - Tx0, PHCE_B, PHOE_B, PHRW_B, JDO 2. IO2, VOH2 and VOL2 apply to the following pins: AD31 - AD0, PAR3 - PAR0, SIZE2 - SIZE0, DR/W, ATTN_B, INTR_B, DBMD, DBML, DBMF, DBMR, DBVC
Data Sheet S12100EJ3V0DS00
17
PD98401A
Capacitance (TA = 25 C, VDD = 0 V, f = 1 MHz)
Parameter Output capacitance Input capacitance I/O capacitance Symbol CO CI CIO f = 1 MHz f = 1 MHz f = 1 MHz Condition MIN. TYP. 7 7 7 MAX. 10 10 10 Unit pF pF pF
AC Characteristics (TA = 0 to +80 C, VDD = 5 V 5 %) AC Test Condition
VDD 2.5 V 0V Test point 2.5 V
Load Condition
D.U.T (Device to be tested)
CL = 50 pF
CLK Input
Parameter CLK cycle time Symbol tCYCLK tCLKH tCLKL tR tF Condition MIN. 30 11 11 4 4 TYP. MAX. 125 Unit ns ns ns ns ns
CLK high level width CLK low level width CLK rise time CLK fall time
tCYCLK tCLKH tF
CLK
tR
tCLKL
18
Data Sheet S12100EJ3V0DS00
PD98401A
PHY Interface (1/2)
(1) Transmission operation
Parameter TCLKTX delay time TCLKTSOC delay time TCLKTEMBL_B delay time Symbol tDTX tDTSOC tDTEN tSFULL tHFULL Condition MIN. 3 3 3 8 1 TYP. MAX. 18 18 18 Unit ns ns ns ns ns
FULL_B setup time
FULL_B hold time
TCLK tDTX Tx7-Tx0 H1 H2 H3 H4 `00H' P1 INVALID P2 P3 P4 P5 P6 P7 P8 P9
TSOC tDTSOC TENBL_B tSFULL FULL_B tHFULL tDTSOC tDTEN tDTEN
H4-H1: ATM Header P9-P1 : Payload Data
Data Sheet S12100EJ3V0DS00
19
PD98401A
PHY Interface (2/2)
(2) Reception operation
Parameter Symbol tSRX tHRX tSRSOC tHRSOC tDREN tSEMPT tHEMPT Condition MIN. 8 1 8 1 3 8 1 18 TYP. MAX. Unit ns ns ns ns ns ns ns
RX setup time
RX hold time
RSOC setup time
RSOC hold time RCLK RENBL_B delay time
EMPTY_B setup time
EMPTY_B hold time
RCLK tSRX Rx7-Rx0 H1 tHRX H2 H3 INVALID H4 H5 P1 P2 INVALID P3 P4 P5 P6 P7
RSOC tSRSOC RENBL_B tSEMPT EMPTY_B H4-H1: ATM Header P7-P1 : Payload Data tHEMPT tHRSOC tDREN tDREN
20
Data Sheet S12100EJ3V0DS00
PD98401A
Host Slave Access (1/2)
(1) Write
Parameter ASEL_B setup time ASEL_B hold time SEL_B setup time SEL_B hold time Address setup time Address hold time Data setup time Data hold time PAR setup time PAR hold time SR/W_B setup time SR/W_B hold time Symbol tSASEL tHASEL tSSEL tHSEL tSDADD tHDADD tSDDAT tHDDAT tSPAR1 tHPAR1 tSSRW tHSRW Condition MIN. 8 3 8 1tCYCLK+3 8 3 8 3 8 3 8 3 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
Write timing
CLK tSASEL ASEL_B tSSEL SEL_B tSDADD AD31-AD0 ADDRESS tSSRW SR/W_B tSPAR1 PAR3-PAR0 (input) tSPAR1 (input) tHSRW tHDADD tSDDAT DATA tHDDAT tHSEL tHASEL
tHPAR1
tHPAR1
Data Sheet S12100EJ3V0DS00
21
PD98401A
Host Slave Access (2/2)
(2) Read
Parameter ASEL_B setup time ASEL_B hold time SEL_B setup time SEL_B hold time Address setup time Address hold time Symbol tSASEL tHASEL tSSEL tHSEL tSDADD tHDADD tDDDAT tFDDAT tSPAR1 tHPAR1 tDPAR1 tFPAR1 tSSRW tHSRW 3 8 3 3 8 3 20 18 Condition MIN. 8 3 8 1tCYCLK+3 8 3 20 18 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CLKdata delay time
CLKdata floating time PAR setup time PAR hold time
CLKPAR delay time
CLKPAR floating time SR/W_B setup time SR/W_B hold time
Read timing
CLK tSASEL ASEL_B tSSEL SEL_B tSDADD AD31-AD0 ADDRESS (input) tSSRW SR/W_B tSPAR1 PAR3-PAR0 (input) tDPAR1 tHPAR1 (output) tFPAR1 tHSRW tHDADD tDDDAT DATA (output) tFDDAT tHSEL tHASEL
22
Data Sheet S12100EJ3V0DS00
PD98401A
DMA Access (1/2)
(1) Write
Parameter CLKATTN_B delay time GNT_B setup time GNT_B hold time CLKDR/W_B delay time CLKSIZE delay time Symbol tDATTN tSGNT tHGNT tDDRW tDSIZE tDSADD tFSADD tDPAR2 tFPAR2 tSRDY tHRDY 3 8 3 3 8 3 3 3 18 18 20 18 20 18 Condition MIN. TYP. MAX. 18 Unit ns ns ns ns ns ns ns ns ns ns ns
CLKaddress delay time
CLKaddress/data floating time
CLKPAR delay time
CLKPAR floating time
RDY_B setup time
RDY_B hold time
Write timing ( Example: 2 word burst)
CLK tDATTN ATTN_B tSGNT GNT_B tDDRW DR/W_B tDSIZE SIZE2-SIZE0 tDSADD AD31-AD0 Hi-Z
ADDRESS (output)
tDATTN
tHGNT
tDDRW
tDSIZE
tFSADD DATA 0 (output) tSRDY
DATA 1 (output)
tFSADD
tHRDY
RDY_B (Normal mode) tSRDY RDY_B (Early mode) tDPAR2 PAR3-PAR0 (output) tFPAR2 (output) tDPAR2 (output) tHRDY
Data Sheet S12100EJ3V0DS00
23
PD98401A
DMA Access (2/2)
(2) Read
Parameter CLKATTN B_delay time GNT_B setup time GNT_B hold time CLKDR/W_B delay time CLKSIZE delay time Symbol tDATTN tSGNT tHGNT tDDRW tDSIZE tDSADD tFSADD tDPAR2 tSRDY tHRDY tSSDAT tHSDAT tSPAR2 tHPAR2 8 3 8 3 8 3 3 8 3 3 3 18 18 20 18 20 Condition MIN. TYP. MAX. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CLKaddress delay time
CLKaddress/data floating time
CLKPAR delay time RDY_B setup time
RDY_B hold time Data setup time Data hold time PAR setup time PAR hold time
Read timing (Example: 2 word burst)
CLK tDATTN ATTN_B tSGNT GNT_B tDDRW DR/W_B tDSIZE SIZE2-SIZE0 tDSADD AD31-AD0 Hi-Z
ADDRESS (output)
tDATTN
tHGNT
tDDRW
tDSIZE
tFSADD
tSSDAT
DATA 0 (input)
tHSDAT
DATA 1 (input)
tSRDY RDY_B (Normal mode) tSRDY RDY_B (Early mode) tDPAR2 PAR3-PAR0 (output) tSPAR2 (input) tHRDY
tHRDY
tHPAR2 (input)
24
Data Sheet S12100EJ3V0DS00
PD98401A
Signals ABRT B, ERR B, and OE_B
Parameter Symbol tSABRT tHABRT tSERR tHERR tDADOE Condition MIN. 8 3 8 3 18 TYP. MAX. Unit ns ns ns ns ns
ABRT_B setup time
ABRT_B hold time
ERR_B setup time
ERR_B hold time
OE_BAD, PAR output
definition time
OE_BAD, PAR Hi-Z definition
time
tFADOE
18
ns
DMA abort/ERR B timing
CLK
ATTN_B
GNT_B tSABRT ABRT_B tHABRT
tSERR ERR_B
tHERR
OE_B timing
tFADOE AD31-AD0 PAR3-PAR0 Hi-Z DATA 0 (Output) DATA 0 (Output) tDADOE
OE_B
Data Sheet S12100EJ3V0DS00
25
PD98401A
Bus Monitoring Signal
Parameter Symbol tDDBMD tDDBML tDDBMF tDDBMR Condition MIN. TYP. MAX. 18 19 19 18 Unit ns ns ns ns
CLKDBMD delay time CLKDBML delay time CLKDBMF delay time CLKDBMR delay time
Bus monitoring signal timing
CLK
ATTN_B tDDBMD DBMD tDDBML DBML tDDBMF DBMF tDDBMR DBMR tDDBMF tDDBML
26
Data Sheet S12100EJ3V0DS00
PD98401A
Control Memory Access (1/2)
(1) Write
Parameter Symbol tSCWE tSCWE2 tCWEL tFCD tDCOE tHCA tHCBE tSCD tFCPAR tSCPAR Condition MIN. 0 0 1tCLKH-2 0 0 0 0 8 0 8 1tCLKL+10 1tCLKL+10 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
CACWE_B setup time CBE_BCWE_B setup time CWE_B low level width CWE_BCD floating time CWE_BCOE_B delay time CA hold time (vs. CWE_B)
CBE_B hold time (vs. CWE_B) CD output time (vs. CWE_B) CWE_BCPAR floating time CPAR output time (vs. CWE_B)
Write timing
CLK
CBE_B3-CBE_B0 tSCWE2 tHCBE
CA17-CA0 tSCWE CWE_B tDCOE COE_B tSCD CD31-CD0 (output) tSCPAR CPAR3-CPAR0 (output) tFCPAR tFCD tCWEL tHCA
Data Sheet S12100EJ3V0DS00
27
PD98401A
Control Memory Access (2/2)
(2) Read
Parameter Symbol tDCDCB tDCDCA tDCDCO tHCDCB tHCDCA tHCDCO tDCPCB tDCPCA tDCPCO tHCPCB tHCPCA tHCPCO 0 0 0 0 0 0 1tCYCLK-15 1tCYCLK-15 1tCYCLK-15 Condition MIN. TYP. MAX. 1tCYCLK-15 1tCYCLK-15 1tCYCLK-15 Unit ns ns ns ns ns ns ns ns ns ns ns ns
CD delay enable time (vs. CBE_B) CD delay enable time (vs. CA) CD delay enable time (vs. COE_B) CD hold time (vs. CBE_B) CD hold time (vs. CA) CD hold time (vs. COE_B) CPAR hold enable time (vs. CBE_B) CPAR hold enable time (vs. CA) CPAR hold enable time (vs. COE_B) CPAR hold time (vs. CBE_B) CPAR hold time (vs. CA) CPAR hold time (vs. COE_B)
Read timing
CLK
CBE_B3-CBE_B0
CA17-CA0
CWE_B
`H'
COE_B tDCDCB tDCDCA tDCDCO CD31-CD0 (input) tHCDCB tHCDCA tHCDCO
CPAR3-CPAR0 tDCPCO tDCPCA tDCPCB
(input) tHCPCO tHCPCA tHCPCB
28
Data Sheet S12100EJ3V0DS00
PD98401A
PHY Status Access (1/2)
(1) Write
Parameter CLKCA delay time Symbol tDPCA tDPHRW tDPHCE tDPCD tFPCD 1tCYCLK-10 Condition MIN. TYP. MAX. 20 20 20 20 1tCYCLK+10 Unit ns ns ns ns ns
CLKPHRW_B delay time CLKPHCE_B delay time
CLKCD delay time PHCE_B CD floating time
Write timing
1 clock CLK tDPCA CA17-CA0 tDPHRW PHRW_B tDPHCE PHCE_B tDPHCE tDPHRW tDPCA 4 clocks 1 clock
PHOE_B
`H'
tDPCD
tFPCD
CD31-CD0
(output)
Data Sheet S12100EJ3V0DS00
29
PD98401A
PHY Status Access (2/2)
(2) Read
Parameter CD setup time CD hold time CLKCA delay time Symbol tSPCD tHPOECD tDPCA tDPHRW tDPHCE tDPHOE Condition MIN. 0 0 20 20 20 20 TYP. MAX. Unit ns ns ns ns ns ns
CLKPHRW_B delay time CLKPHCE_B delay time CLK PHOE_B delay time
Read timing
1 clock CLK tDPCA CA17-CA0 tDPHRW PHRW_B tDPHCE PHCE_B
6 clocks tDPCA
5 clocks
4 clocks
tDPHCE tDPHOE tDPHOE
PHOE_B tSPCD CD31-CD0 (input) tHPOECD
30
Data Sheet S12100EJ3V0DS00
PD98401A
JTAG Boundary Scan
Parameter JCK cycle time JCK high-level width JCK low-level width JMS setup time JMS hold time JDI setup time JDI hold time Capture_DR data input setup time Symbol tCYJCK tJCKH tJCKL tSJMS tHJMS tSJDI tHJDI tSJIN tHJIN tDJOUT tDJDO tJRSTL 1tCYJCK Condition MIN. 100 40 40 10 10 10 10 15 15 25 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
Capture_DR data input hold time JCKUp Date_DR output delay time
JCKJDO delay time JRST_B low-level width
JTAG boundary scan timing
tCYJCK tJCKH JCK tJRSTL JRST_B tSJMS JMS tSJDI JDI tDJDO JDO tSJIN All input tDJOUT All output tHJIN tHJDI tHJMS tJCKL
Data Sheet S12100EJ3V0DS00
31
PD98401A
Others
Parameter SEL_B recovery time SEL_BGNT_B recovery time RDY_BSEL_B recovery time PHINT_B setup time PHINT_B hold time RST_B input pulse width RST_BSEL_B recovery time Symbol tRVSEL tRVSM tRVMS tSPHI tHPHI tRSTL tRSTSL RDY_B mode in normal operation Condition MIN. 2 1 1 8 1 1 20 TYP. MAX. Unit tCYCLK tCYCLK tCYCLK ns ns tCYCLK tCYCLK
Other timing
CLK
SEL_B tRVSEL GNT_B tRVMS tRVSM RDY_B tSPHI PHINT_B tHPHI
tRSTL RST_B tRSTSL SEL_B
32
Data Sheet S12100EJ3V0DS00
PD98401A
4. PACKAGE DRAWINGS
208-PIN PLASTIC QFP (FINE PITCH) (28x28)
A B
156 157 105 104
detail of lead end S CD Q R
208 1
53 52
F G P H I
M
J
K M
S L
NS
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 30.60.2 28.00.2 28.00.2 30.60.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.30.2 0.50.2 0.17 +0.03 -0.07 0.10 3.20.1 0.40.1 55 3.8 MAX.
P208GD-50-LML, MML, SML-6
Data Sheet S12100EJ3V0DS00
33
PD98401A
5. RECOMMENDED SOLDERING CONDITIONS
Solder the product under the following recommended conditions. For details of the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and soldering conditions other than those recommended, consult NEC. Surface Mount Type
PD98401AGD-MML: 208-pin plastic QFP (Fine pitch) (28 x 28 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235 C, Time: 30 seconds max. (210 C min.), Number of times: 2 max., Number of days: 7 Note (Afterwards, prebaking is necessary at 125 C for 36 hours.) Partial heating Pin temperature: 300 C max., Time: 3 seconds max. (per side of device) - Symbol of Recommended Condition IR35-367-2
Note The number of days during which the product can be stored at 25 C, 65 % RH max. after the dry pack has been opened.
34
Data Sheet S12100EJ3V0DS00
PD98401A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S12100EJ3V0DS00
35
PD98401A
NEASCOT-S10 and NEASCOT-S15 are trademarks of NEC Corporation.
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

▲Up To Search▲

Price & Availability of UPD98401A

	To Download UPD98401A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .